CPU Simulator

This tool is designed to simulate the registers and busses inside a Von Neumann CPU for students studying for an A Level Computer Science (OCR Exam board)

It's designed as a visual aid to step through each stage of the fetch-decode-execute cycle so that you can see the purpose of each register and bus within the CPU. The structure of the CPU is designed to look similar to the one featured in the Craig'n'Dave videos which uses a binary version of the LMC instruction set

Settings

Show values as:

Run speed:

Press the step button to see each stage of the fetch, decode execute cycle

RAM

Address	Value
00000000	00000000
00000001	00000000
00000010	00000000
00000011	00000000
00000100	00000000
00000101	00000000
00000110	00000000
00000111	00000000
00001000	00000000
00001001	00000000
00001010	00000000
00001011	00000000
00001100	00000000
00001101	00000000
00001110	00000000
00001111	00000000

CPU

PC

00000000

MAR

00000000

MDR

00000000

ACC

00000000

CIR

00000000

ALU

CU

Decode unit

Opcode	Operand	Instruction
0000	0000	End
0001	address	Add
0010	address	Subtract
0011	address	Store
0101	address	Load
0110	address	Branch Always
0111	address	Branch if ACC = 0
1000	address	Branch if ACC >= 0
1001	0001	Input
1001	0010	Output

This tool has been put together by P.Dring at Fulford School. Please contact me if you have any questions or spot any bugs