CPU Simulator

This tool is designed to simulate the registers and busses inside a Von Neumann CPU for students studying for an A Level Computer Science (OCR Exam board)
It's designed as a visual aid to step through each stage of the fetch-decode-execute cycle so that you can see the purpose of each register and bus within the CPU. The structure of the CPU is designed to look similar to the one featured in the Craig'n'Dave videos which uses a binary version of the LMC instruction set

Settings

Show values as:
Press the step button to see each stage of the fetch, decode execute cycle
Created with Raphaël 2.2.0Address busData busControl bus

RAM

AddressValue
0000000000000000
0000000100000000
0000001000000000
0000001100000000
0000010000000000
0000010100000000
0000011000000000
0000011100000000
0000100000000000
0000100100000000
0000101000000000
0000101100000000
0000110000000000
0000110100000000
0000111000000000
0000111100000000

CPU

PC
00000000
MAR
00000000
MDR
00000000
ACC
00000000
CIR
00000000
ALU
CU

Decode unit

OpcodeOperandInstruction
00000000End
0001addressAdd
0010addressSubtract
0011addressStore
0101addressLoad
0110addressBranch Always
0111addressBranch if ACC = 0
1000addressBranch if ACC >= 0
10010001Input
10010010Output
This tool has been put together by P.Dring at Fulford School. Please contact me if you have any questions or spot any bugs